The present invention relates to electronic circuits, and, more particularly, to a multiplexer with inhibit adaptable to emitter-coupled logic gate arrays.
Gate arrays are semiconductor devices with standard doping layers and customizable metalization layers. Gate arrays allow a design effort to obtain application specific integrated circuits while avoiding the long lead times involved in designing a circuit from scratch. Since they are neither off-the-shelf items, nor entirely customized, gate arrays are considered semi-custom devices. Gate arrays can be fabricated according to a variety of process technologies, for example, complementary metal-on-oxide (CMOS) and bipolar emitter-coupled logic (ECL).
To facilitate custom design, the gate array is divided into a number of transistor groupings or "cells". A cell library defines logic functions which can be implemented in a predetermined number of cells. The cell size is selected by the producer of the gate array blanks to optimize the customization process. The number of transistors per cell should be large enough to provide useful logic functions, and yet not so large as to limit the flexibility of the ultimate design. However, the cell size is made less significant by providing for half-cell or multiple-cell logic functions.
The cell library is dependent on the process technology, e.g., CMOS or ECL, the cell design, characteristics of the associated computer-aided design (CAD) software, and the intended market. However, one common objective for cell libraries is to maximize the functionality per unit cell. As a first approximation, this means minimizing the transistor count for a given function.
However, the problem is more complex than this, since the interconnections among gate array transistors are subject to constraints. Typically, ECL gate array designs require one or more sets of transistors to share collectors; thus not all transistors are "free-standing". An ECL circuit, even though its transistor count is within that of a cell, can still be excluded from the cell library if the number of free-standing transistors exceeds that available for a cell. Thus, in implementing a function, both the free-standing transistor count and the total transistor count must be considered.
Maximizing functionality is especially important for cells which are likely to be repeated many times within a given gate array design. A multiplexer (MUX) cell, for example, may be implemented hundreds of times within a design intended for complex information routing. A multiplexer is basically a switch the output of which is, or is the inverse of, a selected one of several inputs.
A MUX is characterizable by the number of inputs, e.g. there are 2:1 MUXs, 3:1 MUXs, etc. Typically, a MUX includes an output, the several inputs, and select lines. Some MUXs include a provision for an enable or inhibit signal so that there is an option to select none of the inputs. These are important, for example, in computer buses and information exchange networks to avoid contention for shared communications lines.
The present invention is directed to a multiplexer with an inhibit provision for use in an ECL gate array. The inhibit function is typically added to the multiplexer either at the inputs or at the output.
In the first approach, the inhibit function is provided by logically combining the inhibit signal with each input. For example, when each input is ORed with an inhibit logic "1", the output is constant no matter which input is selected. In the case of an ECL 4:1 MUX, this approach could be implemented by paralleling each input gate with an inhibit transistor. The disadvantage of this approach is that it requires an additional active transistor for each input line, and can require four additional collector contacts. The additional contacts are not always available in a gate array and, when available, can slow down the MUX.
The inhibit signal can be combined with the output signal by adding another logic level, and therefore an additional delay. The additional delay can be avoided as far as the data timing is concerned, at the expense of additional free-standing transistors. In the case of an ECL 4:1 MUX, this provides no transistor count advantage over the inhibiting-the-inputs approach.
While, in some cases, the cost of the above approaches is small, in many cases, the free-standing or total transistor count can be exceeded by one transistor. The need for this additional transistor count can require an additional cell, greatly diminishing the functional efficiency of an incorporating design. Furthermore, the available designs can add logic delays and otherwise impair the operating speed of the circuit. The challenge addressed by the present invention is implementing the MUX with inhibit function more efficiently.